We just added two highly informative video clips condensing 13.7 billion years of cosmic activity into 18 minutes - from the gateway of the Big Bang when the basic building blocks of everything from microbes to galaxies were signed, sealed and delivered in the ?first few millionths? of a second, the time line when the fundamental quarks became locked up within the protons and neutrons that form atomic nuclei, to the present day understanding of our universe.
Though less to do with high energy particle physics and cosmic science, it may interest some to review our dedicated web for Gas Flow Management.
Coming soon, CAEN Mod. NV8020 is a 19? X 7U 84TE mixed VME NIM crate equipped with a 1U common fan unit.
The VME section features 6 slots suitable for 6Ux160mm boards, with VME64 compliant backplane. The section is powered by universal AC input switching Power Supply (6U 8TE). The Power distribution is 50A@+5V, 1.5A@-12V, 7.5A@+12V.
The NIM section consists of 7 NIM slots (5 free) provided with pluggable 150W power supply. The Unit is powered by 110 or 220 Vac, 50 ?60 Hz. On the front panel the status of power supply is indicated by green/red LED. Tentative Data
19? x 7U (6+1) enclosure mixed VME/NIM crate
VME section
6 slot for 6U x 160mm VME modules
400W Power Supply
6U 8TE Switching Power Supply (400 W)
VME64 J1/J2 monolithic backplane
NIM section
7 slot NIM (5 free slots)Slot linear power supply (150 W)
An extension to the CAEN family of sampling ADC has arrived and more are coming soon; 7 models for VME64 crates; 5 models for NIM crate, 5 for desktop mount; 3 for PCI slots. In total, 20 models of Waveform Digitizers are already relkeased or coming soon.
The Mod. DT5720 is a "Desktop" module housing a 4 Channel 12 bit 250 MS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities. Input dynamics is 2 Vpp (single ended or differential).
The DC offset of the input signal can be adjusted channel per channel by a programmable 16bit DAC on single ended input version.
The modules feature a front panel clock In and a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read via USB. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM memory buffer (from 1.25 to 10 M Samples/ch) with independent read-write access divided in buffers of programmable size (1 - 1024). Zero suppression and data reduction algorithms allow substantial savings in data amount readout and processing, rejecting samples smaller than programmable thresholds.
The trigger signal can be provided via the front panel input as well as via the software, but it can also be generated internally.
The board houses a USB 2.0 Link able to transfer data at 30 MB/s.
Tentative Data
4 channel
2 Vpp input dynamics (single ended or differential)
12 bit 250 MS/s ADC
Trigger Time stamps
Memory buffer: up to 10 MSample/ch
FPGA for real-time data processing
Zero Suppression and Data Reduction algorithms
Programmable event size and pre-post trigger adjustment
USB 2.0 interface
Firmware upgradeable via USB
Libraries, Demos (C and LabView) and Software tools for Windows and Linux
This will interest scientists managing their department's sub-web or their group's homepage.
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